This invention relates in general to digital logic circuits and more specifically to using combinational logic and control signals at the inputs to logic elements in a programmable logic device.
Programmable logic devices (PLDs) represent a compromise in digital circuit design. By providing a standard architecture that uses many logic elements (LEs) capable of performing basic logic functions, and by allowing flexible interconnection of these logic elements and other resources, a PLD provides a circuit designer with the ability to specify which functions the logic elements perform and the interconnection among logic elements to achieve different design goals. For example, PLDs can be configured to perform tasks such as controllers, processors, and other digital systems. Because a PLD uses predesigned functions, a design implementation may not be as efficient as a fully custom design. However, the time to achieve the design is much less since a new device does not have to be fabricated.
One example of a PLD is the "FLEX" series of devices manufactured by Altera Corporation. An example of a specific device is called the FLEX 10K. A discussion of this device can be found in the Altera Data Book, published by Altera Corporation, 1996, which is incorporated herein by reference. FIG. 1A shows a block diagram of a basic configuration of a FLEX 10K PLD. As shown in FIG. 1A, the PLD 10 includes an embedded array 12 having two embedded array blocks (EABs). The embedded array is used to implement memory and specialized logic functions. For example, random access memory (RAM), read-only memory (ROM), and first-in, first-out (FIFO) functions can be implemented. Each EAB can contribute 100 to 600 gates toward complex logic functions such as multipliers, microcontrollers, state machines, digital signal processing (DSP) functions, etc.
A logic array consisting of logic array blocks (LABs) such as LAB 16 is provided. Each LAB is, in turn, made up of eight logic elements (LEs) 18 and a local interconnect 20. Each LAB can be used to create medium-sized blocks of logic--such as 8-bit counters, address decoders, or state machines--or combinations of LABs can be formed to create larger logic blocks. Each LAB represents about 96 useful gates of logic.
Row and column interconnections are shown such as row interconnect 22 and column interconnect 24. These connection channels provide fast input and output between the input/output elements (IOEs) and LEs.
FIG. 1B is an expanded block diagram of a LAB, for example, LAB 16 shown in FIG. 1A.
As shown in FIG. 1B, each LAB is provided with a LAB local interconnect 40 that provides four input signals to each of the eight LEs comprising the LAB. Also, four LAB control signals 42 are provided to each LE. Each LE is provided with a Carry-In and Cascade-In which are propagated from LE to LE and can be chained to other LEs in other LABs. Output from the LEs is channeled back to LAB local interconnect 40 or can be routed to column or row interconnects for purposes of sending to other LABs, the EABs or IOEs. Routing to other LABs is via the LAB local interconnect 40 connection to the row interconnect or the LAB control signals 42 connection to the row interconnect as shown. In this manner, signals can be shared and distributed among all elements of the PLD.
FIG. 1C shows details of an individual LE, such as LE1 of FIG. 1B. In FIG. 1C, the data signals coming from the LAB local interconnect are shown at 60. Control signals coming from LAB control signals are shown at 62. Similarly, the Carry-In, Cascade-In and outputs from the LE are shown. The LE is, conceptually, the smallest unit of logic in the FLEX 10K architecture. Each LE contains a four-input lookup table (LUT), which is a function generator that can quickly compute any function of four variables. In addition, each LE contains a programmable flipflop with a synchronous enable, a carry chain, and a cascade chain. Each LE drives both column and row interconnects so that outputs from the LE can be routed to other LEs, to the EABs, output pins or other components.
Typical functions that are implemented in a PLD are multipliers, multiplexers, counters, etc. While the PLD is a good compromise in design flexibility and rapid implementation, there are inevitably wasted resources (i.e., gates) in adapting the predefined logic of a PLD to a specific circuit design. For example, in order to implement a 16-bit adder, many single bit summations must occur. Each summation uses an entire LE as shown in FIG. 1D. Other functions such as a clearable up/down counter or multiplexer suffer from similar design constraints that require a large number of LEs to be used to implement very basic operations.
Thus, it is desirable to improve the flexibility of PLDs of the architecture described, or similar architecture, so that operations such as multiplications and other functions can be performed with less gates in the PLD. Additionally, the improvement should not result in an undue increase in the number of gates in the PLD or the complexity of implementing a design in the PLD.